From 00d9e3de8802a4c79ff31b61e0e70961167577f1 Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Tue, 8 Sep 2026 18:23:27 +1000 Subject: [PATCH] Fixed error where assignment was not within a combinational/sequential block --- modules/instruction_classifier.sv | 37 ++++++++++++++++--------------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/modules/instruction_classifier.sv b/modules/instruction_classifier.sv index 2b4861b..07c3ff1 100644 --- a/modules/instruction_classifier.sv +++ b/modules/instruction_classifier.sv @@ -3,23 +3,24 @@ module instruction_classifier(input logic op[5:0], output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F, output logic[0:0] M); - logic [6:0] OUT_1; - casez (op) - 6'b1?????: OUT_1 = 7'b1000000; - 6'b01????: OUT_1 = 7'b0100000; - 6'b001???: OUT_1 = 7'b0010000; - 6'b0001??: OUT_1 = 7'b0001000; - 6'b00001?: OUT_1 = 7'b0000100; - 6'b000001: OUT_1 = 7'b0000010; - 6'b000000: OUT_1 = 7'b0000001; - endcase - - assign R = OUT_1[6]; - assign B1 = OUT_1[5]; - assign J = OUT_1[4]; - assign B2 = OUT_1[3]; - assign I = OUT_1[2]; - assign F = OUT_1[1]; - assign M = OUT_1[0]; + always_comb begin + logic [6:0] OUT_1; + casez (op) + 6'b1?????: OUT_1 = 7'b1000000; + 6'b01????: OUT_1 = 7'b0100000; + 6'b001???: OUT_1 = 7'b0010000; + 6'b0001??: OUT_1 = 7'b0001000; + 6'b00001?: OUT_1 = 7'b0000100; + 6'b000001: OUT_1 = 7'b0000010; + 6'b000000: OUT_1 = 7'b0000001; + endcase + R = OUT_1[6]; + B1 = OUT_1[5]; + J = OUT_1[4]; + B2 = OUT_1[3]; + I = OUT_1[2]; + F = OUT_1[1]; + M = OUT_1[0]; + end endmodule \ No newline at end of file