Fixed error where assignment was not within a combinational/sequential block

modules/instruction_classifier.sv

@@ -3,6 +3,7 @@ module instruction_classifier(input logic op[5:0],
     output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
     output logic[0:0] M);
 
+    always_comb begin
         logic [6:0] OUT_1;
         casez (op)
             6'b1?????: OUT_1 = 7'b1000000;
@@ -14,12 +15,12 @@ module instruction_classifier(input logic op[5:0],
             6'b000000: OUT_1 = 7'b0000001;
         endcase
 
-    assign R  = OUT_1[6];
+        R  = OUT_1[6];
-    assign B1 = OUT_1[5];
+        B1 = OUT_1[5];
-    assign J  = OUT_1[4];
+        J  = OUT_1[4];
-    assign B2 = OUT_1[3];
+        B2 = OUT_1[3];
-    assign I  = OUT_1[2];
+        I  = OUT_1[2];
-    assign F  = OUT_1[1];
+        F  = OUT_1[1];
-    assign M  = OUT_1[0];
+        M  = OUT_1[0];
-
+    end
 endmodule