FPGA_Uni/tests/instruction_classifier_tb.sv at f881a4126b9f0774a5e7413814dec82b6ec4fc4b - FPGA_Uni - Riley's Git Server

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riley 6668969b03

Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v

2026-09-03 16:05:52 +10:00

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Systemverilog

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`#include "instruction_classifier.v"