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dd5d044da326157e032665fae75897e50fc26c62
FPGA_Uni/tests/tests.sv
T
riley a89a66d34d Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00

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Systemverilog
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`include "tests/seven_seg_tb.sv"
`include "tests/lu_tb.sv"
`include "tests/asu_tb.sv"
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