157 lines
6.0 KiB
Systemverilog
157 lines
6.0 KiB
Systemverilog
`ifndef ASS_3_SV
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`define ASS_3_SV
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`include "rom.sv"
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`include "ram.sv"
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`include "register_file.sv"
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`include "instruction_counter.sv"
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`include "control_unit.sv"
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`include "alu.sv"
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`include "shifter.sv"
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`include "sign_extender.sv"
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`include "gatereg.sv"
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`include "hazard_unit.sv"
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module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=9, parameter ramsz=10)(
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input logic [0:0] clk, input logic [0:0] rst
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);
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logic [31:0] regs_out [32];
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// Inputs
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logic [0:0] hazard_m2r_1, hazard_m2r_2;
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logic [0:0] hazard_reg_we_1, hazard_reg_we_2, hazard_reg_we_3;
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logic [4:0] hazard_rt_0, hazard_rt_1;
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logic [4:0] hazard_rs_0, hazard_rs_1;
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logic [4:0] hazard_write_reg_0, hazard_write_reg_1, hazard_write_reg_2;
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// Outputs
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logic [1:0] hazard_forwardAE, hazard_forwardBE;
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logic [0:0] hazard_forwardAD, hazard_forwardBD;
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logic [0:0] hazard_stallF, hazard_stallD;
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logic [0:0] hazard_flushE, hazard_flushD;
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// TODO: too many variables - find what should't be here
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hazard_unit hazard_unit(
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B,
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hazard_rs_0, hazard_rt_0,
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hazard_rs_1, hazard_rt_1,
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hazard_write_reg_0, hazard_reg_we_1, hazard_m2r_1,
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hazard_write_reg_1, hazard_reg_we_2, hazard_m2r_2,
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hazard_write_reg_2, hazard_reg_we_3,
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hazard_stallF, hazard_stallD,
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hazard_forwardAD, hazard_forwardBD,
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hazard_flushE,
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hazard_forwardAE, hazard_forwardBE
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);
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logic [2**width-1:0] pc_addr, pc_addr_1, pc_addr_2;
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logic [2**width-1:0] pc_addr_write;
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logic [0:0] pc_we;
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instruction_counter #(width) PC (clk, rst, ~hazard_stallF, pc_we, pc_addr_write, pc_addr);
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gatereg #(width, 1) gate_pc_addr(clk, rst | hazard_flushD, ~hazard_stallF, pc_addr, pc_addr_1);
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logic [2**width-1:0] rom_rd;
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logic [2**width-1:0] instruction, instruction_1;
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rom #(progsrc, romsz, width) ROM (pc_addr_1[romsz-1:0], rom_rd);
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gatereg #(width, 1) gate_instruction(clk, rst | hazard_flushD, ~hazard_stallD, rom_rd, instruction);
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gatereg #(width, 1) gate_instruction_1(clk, rst | hazard_flushE, 1'b1, instruction, instruction_1);
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logic [0:0] cu_m2r, cu_m2w, cu_alu_src, cu_rdst, cu_rw;
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logic [0:0] cu_m2w_1, cu_rw_1, cu_m2r_1;
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logic [0:0] cu_m2r_2, cu_rw_2;
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logic [3:0] cu_alu_fn, ALU_FN;
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logic [0:0] B, MEM_WE, RDST, ALU_SRC, REG_WE, REGW_MEM_OR_RD;
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control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
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cu_m2r, cu_m2w, B, cu_alu_fn, cu_alu_src, cu_rdst, cu_rw
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);
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gatereg #(0, 1) gate_cu_rdst (clk, rst | hazard_flushE, 1'b1, cu_rdst, RDST);
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gatereg #(0, 1) gate_cu_alu_src (clk, rst | hazard_flushE, 1'b1, cu_alu_src, ALU_SRC);
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gatereg #(2, 1) gate_cu_alu_fn (clk, rst | hazard_flushE, 1'b1, cu_alu_fn, ALU_FN);
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gatereg #(0, 1) gate_cu_m2w(clk, rst | hazard_flushE, 1'b1, cu_m2w, cu_m2w_1);
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gatereg #(0, 1) gate_cu_rw(clk, rst | hazard_flushE, 1'b1, cu_rw, cu_rw_1);
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gatereg #(0, 1) gate_cu_m2r(clk, rst | hazard_flushE, 1'b1, cu_m2r, cu_m2r_1);
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gatereg #(0, 1) gate_cu_m2r_1 (clk, rst, 1'b1, cu_m2r_1, cu_m2r_2);
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gatereg #(0, 1) gate_cu_m2w_1 (clk, rst, 1'b1, cu_m2w_1, MEM_WE);
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gatereg #(0, 1) gate_cu_rw_1 (clk, rst, 1'b1, cu_rw_1, cu_rw_2);
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gatereg #(0, 1) gate_cu_m2r_2 (clk, rst, 1'b1, cu_m2r_2, REGW_MEM_OR_RD);
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gatereg #(0, 1) gate_cu_rw_2 (clk, rst, 1'b1, cu_rw_2, REG_WE);
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assign hazard_m2r_1 = cu_m2r_2;
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assign hazard_m2r_2 = REGW_MEM_OR_RD;
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assign hazard_reg_we_1 = cu_rw_1;
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assign hazard_reg_we_2 = cu_rw_2;
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assign hazard_reg_we_3 = REG_WE;
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logic [2**width-1:0] regf_rs, regf_rs_1;
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logic [2**width-1:0] regf_rt, regf_rt_1, regf_rt_2;
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logic [7:0] regf_a3, regf_a3_1, regf_a3_2;
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logic [2**width-1:0] rd, rd_mem, rd_alu;
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assign rd = (REGW_MEM_OR_RD) ? rd_mem : rd_alu;
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assign regf_a3 = (RDST) ? instruction_1[15:11] : instruction_1[20:16];
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gatereg #(3, 1) gate_regf_a3 (clk, rst, 1'b1, regf_a3, regf_a3_1);
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gatereg #(3, 1) gate_regf_a3_1 (clk, rst, 1'b1, regf_a3_1, regf_a3_2);
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register_file #(width, 5) REGS (
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~clk, REG_WE,
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regf_a3_2[4:0], rd,
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instruction[25:21], regf_rs,
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instruction[20:16], regf_rt,
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regs_out
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);
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gatereg #(width, 1) gate_regf_rs(clk, rst | hazard_flushE, 1'b1, regf_rs, regf_rs_1);
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gatereg #(width, 1) gate_regf_rt(clk, rst | hazard_flushE, 1'b1, regf_rt, regf_rt_1);
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assign hazard_write_reg_0 = regf_a3;
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assign hazard_write_reg_1 = regf_a3_1;
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assign hazard_write_reg_2 = regf_a3_2;
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assign hazard_rs_0 = instruction[25:21];
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assign hazard_rt_0 = instruction[20:16];
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assign hazard_rs_1 = instruction_1[25:21];
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assign hazard_rt_1 = instruction_1[20:16];
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gatereg #(width, 1) gate_regf_rt_1(clk, rst, 1'b1, regf_rt_1, regf_rt_2); // TODO: Remove - is WriteDataE, not rt
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logic [2**width-1:0] sign_ext_imm, rt_imm;
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sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
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gatereg #(width, 1) gate_sign_ext_imm(clk, rst | hazard_flushE, 1'b1, sign_ext_imm, rt_imm);
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// Inputs
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logic [2**width-1:0] alu_in_a, alu_in_b;
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always_comb begin
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case (hazard_forwardAE)
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2'b00: alu_in_a = regf_rs_1;
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2'b01: alu_in_a = rd;
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2'b10: alu_in_a = alu_out_1;
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default: alu_in_a = regf_rs_1;
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endcase
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case (hazard_forwardBE)
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2'b00: alu_in_b = regf_rt_1;
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2'b01: alu_in_b = rd;
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2'b10: alu_in_b = alu_out_1;
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default: alu_in_b = regf_rt_1;
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endcase
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end
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// Outputs
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logic [2**width-1:0] alu_out, alu_out_1, alu_out_2;
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logic [3:0] alu_flags, alu_flags_1;
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alu #(width) ALU (ALU_FN, alu_in_a, (ALU_SRC) ? rt_imm : alu_in_b, alu_out, alu_flags[2:0]);
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gatereg #(width, 1) gate_alu_out (clk, rst, 1'b1, alu_out, alu_out_1);
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gatereg #(width, 1) gate_alu_out_1 (clk, rst, 1'b1, alu_out_1, alu_out_2);
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gatereg #(2, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
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assign rd_alu = alu_out_2;
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logic [2**width-1:0] new_pc_addr;
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assign new_pc_addr = (sign_ext_imm << 2) + pc_addr_1;
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assign pc_addr_write = new_pc_addr;
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assign pc_we = B & ((hazard_forwardAD ? alu_out_1 : regf_rs) == (hazard_forwardBD ? alu_out_1 : regf_rt));
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assign hazard_flushD = pc_we;
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logic [2**width-1:0] mem_out, mem_out_1;
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ram #(ramsz, width) RAM (clk, rst, alu_out_1[ramsz-1:0], MEM_WE, alu_in_b, mem_out);
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gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
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assign rd_mem = mem_out_1;
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endmodule
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`endif
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