46 lines
1.4 KiB
Plaintext
46 lines
1.4 KiB
Plaintext
# Loading project Assignment_1_Q2
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# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini
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# Loading project Assignment_1_Q3
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# Compile of asu.sv was successful.
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# Compile of asu_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.asu_tb
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# vsim work.asu_tb
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# Start time: 15:16:49 on Sep 10,2026
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# Loading sv_std.std
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# Loading work.asu_tb
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# Loading work.asu
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add wave -position end sim:/asu_tb/A
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add wave -position end sim:/asu_tb/B
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add wave -position end sim:/asu_tb/C
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add wave -position end sim:/asu_tb/Cout
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add wave -position end sim:/asu_tb/Cin
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run
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# Beginning ASU tests
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# [38;5;10mAll ASU tests passing[m
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add wave -position end sim:/asu_tb/op
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run
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quit -sim
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# End time: 15:19:15 on Sep 10,2026, Elapsed time: 0:02:26
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# Errors: 0, Warnings: 5
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# Compile of asu.sv was successful.
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# Compile of asu_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.asu_tb
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# vsim work.asu_tb
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# Start time: 15:20:10 on Sep 10,2026
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# Loading sv_std.std
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# Loading work.asu_tb
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# Loading work.asu
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add wave -position end sim:/asu_tb/A
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add wave -position end sim:/asu_tb/B
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add wave -position end sim:/asu_tb/C
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add wave -position end sim:/asu_tb/Cout
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add wave -position end sim:/asu_tb/Cin
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add wave -position end sim:/asu_tb/op
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run
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# Beginning ASU tests
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# [38;5;10mAll ASU tests passing[m
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# End time: 15:24:25 on Sep 10,2026, Elapsed time: 0:04:15
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# Errors: 0, Warnings: 2
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