# Loading project Assignment_1_Q2
# reading /home/oliver/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini
# Loading project Assignment_1_Q3
# Compile of asu.sv was successful.
# Compile of asu_tb.sv was successful.
# 2 compiles, 0 failed with no errors.
vsim work.asu_tb
# vsim work.asu_tb 
# Start time: 15:16:49 on Sep 10,2026
# Loading sv_std.std
# Loading work.asu_tb
# Loading work.asu
add wave -position end  sim:/asu_tb/A
add wave -position end  sim:/asu_tb/B
add wave -position end  sim:/asu_tb/C
add wave -position end  sim:/asu_tb/Cout
add wave -position end  sim:/asu_tb/Cin
run
# Beginning ASU tests
# All ASU tests passing
add wave -position end  sim:/asu_tb/op
run
quit -sim
# End time: 15:19:15 on Sep 10,2026, Elapsed time: 0:02:26
# Errors: 0, Warnings: 5
# Compile of asu.sv was successful.
# Compile of asu_tb.sv was successful.
# 2 compiles, 0 failed with no errors.
vsim work.asu_tb
# vsim work.asu_tb 
# Start time: 15:20:10 on Sep 10,2026
# Loading sv_std.std
# Loading work.asu_tb
# Loading work.asu
add wave -position end  sim:/asu_tb/A
add wave -position end  sim:/asu_tb/B
add wave -position end  sim:/asu_tb/C
add wave -position end  sim:/asu_tb/Cout
add wave -position end  sim:/asu_tb/Cin
add wave -position end  sim:/asu_tb/op
run
# Beginning ASU tests
# All ASU tests passing
# End time: 15:24:25 on Sep 10,2026, Elapsed time: 0:04:15
# Errors: 0, Warnings: 2