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FPGA_Uni
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9d0c7011ce3a6e24b9799b60eedd75502a4b0300
FPGA_Uni
/
Quartus
/
A1_Q1
/
db
/
seven_seg.tiscmp.slow_1100mv_0c.ddb
T
TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
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