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9d0c7011ce3a6e24b9799b60eedd75502a4b0300
FPGA_Uni
/
Quartus
T
History
TroubleElectrical
9d0c7011ce
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
..
A1_Q1
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q2
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q3
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q4
Updated ALU (Q4) with 7seg and confirmed operation on board
2026-09-15 19:05:04 +10:00
A1_Q5
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
A1_Q6
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
