27 lines
721 B
Systemverilog
27 lines
721 B
Systemverilog
`ifndef REGISTER_FILE_H
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`define REGISTER_FILE_H
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module register_file #(parameter width=5, parameter nregs=32)(
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input logic [0:0] clk, input logic[0:0] we,
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input logic [$clog(nregs)-1:0] WA, input logic [2**width-1:0] WD,
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input logic [$clog(nregs)-1:0] RA1, output logic [2**width-1:0] RD1,
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input logic [$clog(nregs)-1:0] RA2, output logic [2**width-1:0] RD2
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);
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localparam BW = 2**width;
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logic [2**width-1:0] regs[nregs];
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initial begin
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regs[0] = {(2**width){1'b0}};
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end
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always_ff @(posedge clk) begin
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if (we & (WA != {(2**width){1'b0}} )) begin
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regs[WA] <= WD;
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end
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end
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assign RD1 = regs[RA1];
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assign RD2 = regs[RA2];
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endmodule
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`endif
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