25 lines
680 B
Systemverilog
25 lines
680 B
Systemverilog
module rom #(addrwidth=9, datawidth=5)(
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input logic [0:0] clk,
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input logic [2**addrwidth-1:0] addr,
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input logic [0:0] we,
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input logic [datawidth-1:0] data_in,
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output logic [datawidth-1:0] data_out
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);
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logic [7:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
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// NOTE: Possible issue with assignments still pending by end of initial block
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initial begin
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for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin
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mem[ADDR] <= 8'b0;
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end
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end
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always_ff(@posedge clk) begin
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if (we) begin
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mem[addr] <= data_in;
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end
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end
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assign data_out = mem[addr];
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endmodule; |