15 lines
391 B
Systemverilog
15 lines
391 B
Systemverilog
`include "rom.sv"
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module ByteIM #(parameter m=5,n=2) (
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input logic [m-1:0] Ad,
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output logic [(2**n)*8-1:0] Dout );
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// 2**n byte wide words
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// m bit wide byte address
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// 2**m bytes of memory
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// 2**(m-n) memory words
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// 2**(n+3) bit wide words
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// Reads the whole word that contains the addressed byte
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ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
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endmodule
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