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riley 5ca004e1f7 Added progsrc string parameter for the hazard and nohazard testbenches to be able to specify what program to run. Added hazard unit and connected it up. Modified pipeline gate/sync registers to disable and/or reset when the hazard unit requests it. 
Modified ALU inputs to allow the hazard unit to route a just-completed calculation back around.
2026-11-12 12:36:57 +11:00
asm
Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62).
2026-11-05 16:15:06 +11:00
ModelSim
Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2.
2026-11-08 12:32:40 +11:00
modules
Added progsrc string parameter for the hazard and nohazard testbenches to be able to specify what program to run. Added hazard unit and connected it up. Modified pipeline gate/sync registers to disable and/or reset when the hazard unit requests it.
2026-11-12 12:36:57 +11:00
Quartus
Added Hazard Unit file (tested compiling correctly) labelled variables inside off of the Assignment 3 Questions PDF Figure 2.
2026-11-08 12:32:40 +11:00
Submission
Added Assignment 2 submission zip file
2026-10-16 15:09:48 +11:00
tests
Updated tests.sv to not perform prior module tests. Seperated testbenches for hazard and nohazard tests.
2026-11-12 12:33:24 +11:00
.gitignore
Created general project structure. Only seven segment, logic unit and adder/subtractor modules and tests implemented
2026-09-03 15:25:07 +10:00
isv.py
Added python script for invoking icarus verilog. This script has three subcommands; submit, test_submit and test. test is equivalent to the run.bat shell script, submit generates a single-file verilog source suitable for submission. test_submit will run all generated submission testbenches to verify that nothing was broken.
2026-09-15 22:00:02 +10:00
README.md
Initial commit
2026-09-03 15:04:27 +10:00
run.bat
Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
2026-09-03 16:32:56 +10:00

README.md

FPGA_Uni

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