TroubleElectrical 5d9e7f541e Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00

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A1_Q1

Added 4 digit 7seg display module (confirmed working for now),

2026-10-13 16:32:15 +11:00

A1_Q2

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

A1_Q3

Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board

2026-09-15 16:52:48 +10:00

A1_Q4

Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)

2026-09-15 19:43:28 +10:00

A1_Q5

Implemented instruction classifier on board (Q6) and added blank submission files (for now)

2026-09-15 20:00:35 +10:00

A1_Q6

Updated register_file.sv with proper naming scheme and 32bit width

2026-10-08 15:10:40 +11:00

A2

Updated RAM code to make sure Bus width is 32 bits

2026-10-16 11:32:47 +11:00