122 lines
8.0 KiB
Plaintext
122 lines
8.0 KiB
Plaintext
Flow report for assignment2
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Thu Oct 15 15:04:20 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Flow Summary
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3. Flow Settings
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4. Flow Non-Default Global Settings
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5. Flow Elapsed Time
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6. Flow OS Summary
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7. Flow Log
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8. Flow Messages
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9. Flow Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2025 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus Prime License Agreement,
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the Altera IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Altera and sold by Altera or its authorized distributors. Please
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refer to the Altera Software License Subscription Agreements
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on the Quartus Prime software download page.
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+-------------------------------------------------------------------------------+
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; Flow Summary ;
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+-----------------------------+-------------------------------------------------+
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; Flow Status ; Flow Failed - Thu Oct 15 15:04:20 2026 ;
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; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
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; Revision Name ; assignment2 ;
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; Top-level Entity Name ; assignment2 ;
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; Family ; Cyclone V ;
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; Device ; 5CGXFC5C6F27C7 ;
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; Timing Models ; Final ;
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; Logic utilization (in ALMs) ; N/A until Partition Merge ;
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; Total registers ; N/A until Partition Merge ;
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; Total pins ; N/A until Partition Merge ;
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; Total virtual pins ; N/A until Partition Merge ;
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; Total block memory bits ; N/A until Partition Merge ;
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; Total PLLs ; N/A until Partition Merge ;
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; Total DLLs ; N/A until Partition Merge ;
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+-----------------------------+-------------------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 10/15/2026 15:04:10 ;
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; Main task ; Compilation ;
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; Revision Name ; assignment2 ;
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+-------------------+---------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
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; COMPILER_SIGNATURE_ID ; 268883478169649.179203705005251 ; -- ; -- ; -- ;
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
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; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
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; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; <None> ; -- ; -- ;
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; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
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; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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; NUM_PARALLEL_PROCESSORS ; 2 ; -- ; -- ; -- ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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; VERILOG_MACRO ; QUARTUS_SYNTH ; -- ; -- ; -- ;
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+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 412 MB ; 00:00:24 ;
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; Total ; 00:00:10 ; -- ; -- ; 00:00:24 ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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+---------------------------------------------------------------------------------------+
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; Flow OS Summary ;
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+----------------------+---------------------+------------+------------+----------------+
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; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
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+----------------------+---------------------+------------+------------+----------------+
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; Analysis & Synthesis ; ollies-ThinkPad-X1C ; Linux Mint ; 22 ; x86_64 ;
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+----------------------+---------------------+------------+------------+----------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
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