37 lines
1.2 KiB
Systemverilog
37 lines
1.2 KiB
Systemverilog
`ifndef ALU_H_SV
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`define ALU_H_SV
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`include "asu.sv"
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`include "lu.sv"
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// flags[0:0] = Cout
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// flags[1:1] = Overflow
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module alu #(parameter width=2)(input logic [3:0] op,
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input logic [2**width-1:0] A, input logic [2**width-1:0] B,
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output logic [2**width-1:0] OUT_1, output logic[1:0] flags);
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logic [0:0] asu_op;
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logic [2**width-1:0] asu_out;
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logic [1:0] asu_flags;
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asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
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logic [2**width-1:0] lu_out;
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lu #(width) logic_unit(op[1:0], A, B, lu_out);
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always_comb begin
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case (op)
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4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
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4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
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4'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
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4'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
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4'b0100: OUT_1 = lu_out;
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4'b0101: OUT_1 = lu_out;
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4'b0110: OUT_1 = lu_out;
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4'b0111: OUT_1 = lu_out;
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4'b1010: OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]) & {{(width-1){1'b0}}, 1'b1};
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4'b1011: OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1};
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default: OUT_1 = {(2**width){1'b0}};
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endcase
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end
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endmodule
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`endif |