62 lines
1.1 KiB
Plaintext
62 lines
1.1 KiB
Plaintext
m255
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K4
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z2
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!s11f vlog 2020.1 2020.02, Feb 28 2020
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13
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!s112 1.1
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!i10d 8192
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!i10e 25
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!i10f 100
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cModel Technology
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d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
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vlu
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Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
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Z1 !s110 1788849038
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!i10b 1
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!s100 nmDP9zlMCJDa@W3_FY5m[2
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Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
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Il^hWCV0VAo9mz6NG=G9=51
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Z3 VDg1SIo80bB@j0V0VzS_@n1
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S1
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Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
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w1788845636
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8lu.sv
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Flu.sv
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!i122 6
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L0 1 16
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Z5 OV;L;2020.1;71
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r1
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!s85 0
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31
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Z6 !s108 1788849037.000000
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!s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
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Z7 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
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!i113 1
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Z8 o-work work -sv
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Z9 tCvgOpt 0
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vlu_tb
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R0
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R1
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!i10b 1
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!s100 gdCQZUG[6;:5f<I_jIOd?1
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R2
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IOAk[D29KmDQ0<F@G9G][k3
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R3
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S1
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R4
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w1788848626
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8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
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F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
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!i122 6
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L0 3 57
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R5
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r1
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!s85 0
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31
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R6
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Z10 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
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R7
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!i113 1
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R8
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R9
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