18 lines
7.6 KiB
Plaintext
18 lines
7.6 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1791864437215 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1791864437215 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 13 15:07:17 2026 " "Processing started: Tue Oct 13 15:07:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1791864437215 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864437215 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864437215 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1791864437534 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1791864437534 ""}
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{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../rom.sv assignment2.sv(5) " "Verilog HDL File I/O error at assignment2.sv(5): can't open Verilog Design File \"../../rom.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 5 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446822 ""}
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{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../ram.sv assignment2.sv(6) " "Verilog HDL File I/O error at assignment2.sv(6): can't open Verilog Design File \"../../ram.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 6 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
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{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../register_file.sv assignment2.sv(7) " "Verilog HDL File I/O error at assignment2.sv(7): can't open Verilog Design File \"../../register_file.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 7 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
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{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_counter.sv assignment2.sv(8) " "Verilog HDL File I/O error at assignment2.sv(8): can't open Verilog Design File \"../../instruction_counter.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 8 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446823 ""}
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{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_classifier.sv assignment2.sv(9) " "Verilog HDL File I/O error at assignment2.sv(9): can't open Verilog Design File \"../../instruction_classifier.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 9 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446824 ""}
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{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../instruction_module_classifier.sv assignment2.sv(10) " "Verilog HDL File I/O error at assignment2.sv(10): can't open Verilog Design File \"../../instruction_module_classifier.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 10 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446824 ""}
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{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../alu.sv assignment2.sv(11) " "Verilog HDL File I/O error at assignment2.sv(11): can't open Verilog Design File \"../../alu.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 11 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
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{ "Error" "EVRFX_VERI_CANT_OPEN_DESIGN_FILE" "../../shifter.sv assignment2.sv(12) " "Verilog HDL File I/O error at assignment2.sv(12): can't open Verilog Design File \"../../shifter.sv\"" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 12 0 0 } } } 0 10054 "Verilog HDL File I/O error at %2!s!: can't open Verilog Design File \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
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{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "assignment2 assignment2.sv(26) " "Ignored design unit \"assignment2\" at assignment2.sv(26) due to previous errors" { } { { "../../modules/assignment2.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" 26 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1791864446825 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864446826 ""}
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{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 9 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 9 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 13 15:07:26 2026 " "Processing ended: Tue Oct 13 15:07:26 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1791864446879 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864446879 ""}
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{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 11 s 1 " "Quartus Prime Full Compilation was unsuccessful. 11 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1791864447553 ""}
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