TroubleElectrical
25a953cdc6
Added Inputs for displaying registers / Program Counter high and low bits, Assigned pins for Display digits, inputs (Labeled HID) and the clk button
95 lines
6.1 KiB
Plaintext
95 lines
6.1 KiB
Plaintext
EDA Netlist Writer report for assignment2
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Tue Oct 13 16:19:10 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. EDA Netlist Writer Summary
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3. Simulation Settings
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4. Simulation Generated Files
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5. EDA Netlist Writer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2025 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus Prime License Agreement,
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the Altera IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Altera and sold by Altera or its authorized distributors. Please
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refer to the Altera Software License Subscription Agreements
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on the Quartus Prime software download page.
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+-------------------------------------------------------------------+
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; EDA Netlist Writer Summary ;
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+---------------------------+---------------------------------------+
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; EDA Netlist Writer Status ; Successful - Tue Oct 13 16:19:10 2026 ;
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; Revision Name ; assignment2 ;
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; Top-level Entity Name ; assignment2 ;
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; Family ; Cyclone V ;
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; Simulation Files Creation ; Successful ;
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+---------------------------+---------------------------------------+
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+----------------------------------------------------------------------------------------------------------------------------------------+
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; Simulation Settings ;
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+---------------------------------------------------------------------------------------------------+------------------------------------+
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; Option ; Setting ;
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+---------------------------------------------------------------------------------------------------+------------------------------------+
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; Tool Name ; Questa Altera FPGA (SystemVerilog) ;
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; Generate functional simulation netlist ; On ;
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; Truncate long hierarchy paths ; Off ;
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; Map illegal HDL characters ; Off ;
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; Flatten buses into individual nodes ; Off ;
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; Maintain hierarchy ; Off ;
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; Bring out device-wide set/reset signals as ports ; Off ;
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; Enable glitch filtering ; Off ;
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; Do not write top level VHDL entity ; Off ;
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; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
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; Architecture name in VHDL output netlist ; structure ;
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; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
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; Generate third-party EDA tool command script for gate-level simulation ; Off ;
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+---------------------------------------------------------------------------------------------------+------------------------------------+
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+---------------------------------------------------------------------------------------+
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; Simulation Generated Files ;
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+---------------------------------------------------------------------------------------+
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; Generated Files ;
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+---------------------------------------------------------------------------------------+
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; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/assignment2.svo ;
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+---------------------------------------------------------------------------------------+
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+-----------------------------+
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; EDA Netlist Writer Messages ;
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+-----------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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Info: Processing started: Tue Oct 13 16:19:09 2026
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Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off assignment2 -c assignment2
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (204019): Generated file assignment2.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A2/simulation/questa/" for EDA simulation tool
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Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 670 megabytes
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Info: Processing ended: Tue Oct 13 16:19:10 2026
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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