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25a953cdc6829ee5a716649c0ffb0ac014668c88
FPGA_Uni/Quartus
T
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TroubleElectrical 25a953cdc6 Added 4 digit 7seg display module (confirmed working for now),
Added Inputs for displaying registers / Program Counter high and low bits,
Assigned pins for Display digits, inputs (Labeled HID) and the clk button
2026-10-13 16:32:15 +11:00
..
A1_Q1
Added 4 digit 7seg display module (confirmed working for now),
2026-10-13 16:32:15 +11:00
A1_Q2
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q3
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
A1_Q4
Updated shifter (Q5) to use proper 2**width approach and corrected the logic such that C is width bits wide, and b is 2**width (as defined in Q5 B)
2026-09-15 19:43:28 +10:00
A1_Q5
Implemented instruction classifier on board (Q6) and added blank submission files (for now)
2026-09-15 20:00:35 +10:00
A1_Q6
Updated register_file.sv with proper naming scheme and 32bit width
2026-10-08 15:10:40 +11:00
A2
Added 4 digit 7seg display module (confirmed working for now),
2026-10-13 16:32:15 +11:00
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