47 lines
2.5 KiB
Plaintext
47 lines
2.5 KiB
Plaintext
# Loading project Assignment_1_Q2
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# Compile of lu.sv was successful.
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# Compile of lu_tb.sv failed with 1 errors.
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# 2 compiles, 1 failed with 1 error.
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# Compile of lu_tb.sv failed with 1 errors.
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# Compile of lu.sv was successful.
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# Compile of lu_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.lu_tb
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# vsim work.lu_tb
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# Start time: 16:26:37 on Sep 08,2026
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# Loading sv_std.std
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# Loading work.lu_tb
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# Loading work.lu
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# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'. Expected 4, found 0.
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# Time: 0 ps Iteration: 0 Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
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# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
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# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
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# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
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# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
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add wave -position end sim:/lu_tb/op
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add wave -position end sim:/lu_tb/A
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add wave -position end sim:/lu_tb/A
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add wave -position end sim:/lu_tb/B
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add wave -position end sim:/lu_tb/C
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quit -sim
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# End time: 16:28:07 on Sep 08,2026, Elapsed time: 0:01:30
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# Errors: 0, Warnings: 12
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# Compile of lu.sv was successful.
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# Compile of lu_tb.sv was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.lu_tb
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# vsim work.lu_tb
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# Start time: 16:30:51 on Sep 08,2026
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# Loading sv_std.std
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# Loading work.lu_tb
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# Loading work.lu
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# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'dut'. Expected 4, found 0.
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# Time: 0 ps Iteration: 0 Instance: /lu_tb/dut File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv Line: 10
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# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'op'.
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# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'A'.
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# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'B'.
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# ** Warning: (vsim-3722) /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv(10): [TFMPC] - Missing connection for port 'Y'.
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quit -sim
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# End time: 16:31:17 on Sep 08,2026, Elapsed time: 0:00:26
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# Errors: 0, Warnings: 7
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