riley 38fa35fccd Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module

2026-11-05 14:10:13 +11:00

..

alu_tb.sv

Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag

2026-10-13 21:34:25 +11:00

asu_tb.sv

Updated default ASU testbench width to be 4-bit to align with seven segment width for demo

2026-09-15 21:28:01 +10:00

instruction_classifier_tb.sv

Updated instruction classifier to use combinational logic with a depth of 3 gates (AND, XNOR, HAND)

2026-09-13 23:35:05 +10:00

lu_tb.sv

Added comments to Logic Unit (Q2) and added to submission file

2026-09-16 12:38:06 +10:00

lu_tb.sv.bak

Added ModelSim folder (and have to add files into it as to allow for different testbench code)

2026-09-08 16:32:01 +10:00

mips_pipelined.sv

Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module

2026-11-05 14:10:13 +11:00

mips_singlecycle.sv

Renamed MIPS test to be a single cycle test

2026-11-04 15:42:52 +11:00

seven_seg_tb.sv

Updated seven segment test bench to reflect prior commit

2026-09-03 16:58:11 +10:00

shifter_tb.sv

Updated shifter testbench to work with 2^n widths rather than bitwidths.

2026-09-15 21:29:47 +10:00

tests.sv

Fixed initialisation bug and compilation error in gatereg module. Added mips_pipelined to test suite. Fixed several bugs in assignment3 MIPS module

2026-11-05 14:10:13 +11:00