45 lines
833 B
Systemverilog
45 lines
833 B
Systemverilog
`ifndef SEVEN_SEG_4_H_SV
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`define SEVEN_SEG_4_H_SV
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`include "seven_seg.sv"
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module seven_seg_4digit (
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input logic [15:0] num,
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output logic [7:0] segments0,
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output logic [7:0] segments1,
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output logic [7:0] segments2,
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output logic [7:0] segments3
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);
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// Rightmost digit
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seven_seg digit0 (
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.num(num[3:0]),
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.rbi_inv(1'b1),
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.segments(segments0)
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);
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// Second digit from right
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seven_seg digit1 (
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.num(num[7:4]),
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.rbi_inv(1'b1),
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.segments(segments1)
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);
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// Third digit from right
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seven_seg digit2 (
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.num(num[11:8]),
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.rbi_inv(1'b1),
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.segments(segments2)
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);
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// Leftmost digit
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seven_seg digit3 (
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.num(num[15:12]),
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.rbi_inv(1'b1),
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.segments(segments3)
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);
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endmodule
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`endif
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