228 lines
9.2 KiB
Plaintext
228 lines
9.2 KiB
Plaintext
/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module shifter
|
|
|
|
Top level modules:
|
|
shifter
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/rom.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module rom
|
|
|
|
Top level modules:
|
|
rom
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module instruction_classifier
|
|
|
|
Top level modules:
|
|
instruction_classifier
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module seven_seg
|
|
|
|
Top level modules:
|
|
seven_seg
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ram.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module ram
|
|
|
|
Top level modules:
|
|
ram
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/control_unit.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module instruction_classifier
|
|
-- Compiling module control_unit
|
|
|
|
Top level modules:
|
|
control_unit
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/mips.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module rom
|
|
-- Compiling module ram
|
|
-- Compiling module register_file
|
|
-- Compiling module instruction_counter
|
|
-- Compiling module instruction_classifier
|
|
-- Compiling module control_unit
|
|
-- Compiling module asu
|
|
-- Compiling module lu
|
|
-- Compiling module alu
|
|
-- Compiling module shifter
|
|
-- Compiling module sign_extender
|
|
-- Compiling module seven_seg
|
|
-- Compiling module seven_seg_4digit
|
|
-- Compiling module assignment2
|
|
-- Compiling module mips_tb
|
|
|
|
Top level modules:
|
|
shifter
|
|
seven_seg_4digit
|
|
mips_tb
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module asu
|
|
|
|
Top level modules:
|
|
asu
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module lu
|
|
|
|
Top level modules:
|
|
lu
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/shifter_tb.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module shifter
|
|
-- Compiling module shifter_tb
|
|
|
|
Top level modules:
|
|
shifter_tb
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment2.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module rom
|
|
-- Compiling module ram
|
|
-- Compiling module register_file
|
|
-- Compiling module instruction_counter
|
|
-- Compiling module instruction_classifier
|
|
-- Compiling module control_unit
|
|
-- Compiling module asu
|
|
-- Compiling module lu
|
|
-- Compiling module alu
|
|
-- Compiling module shifter
|
|
-- Compiling module sign_extender
|
|
-- Compiling module seven_seg
|
|
-- Compiling module seven_seg_4digit
|
|
-- Compiling module assignment2
|
|
|
|
Top level modules:
|
|
shifter
|
|
seven_seg_4digit
|
|
assignment2
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_tb.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module seven_seg
|
|
-- Compiling module seven_seg_tb
|
|
|
|
Top level modules:
|
|
seven_seg_tb
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module lu
|
|
-- Compiling module lu_tb
|
|
|
|
Top level modules:
|
|
lu_tb
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/asu_tb.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module asu
|
|
-- Compiling module asu_tb
|
|
|
|
Top level modules:
|
|
asu_tb
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/gatereg.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module gatereg
|
|
|
|
Top level modules:
|
|
gatereg
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/sign_extender.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module sign_extender
|
|
|
|
Top level modules:
|
|
sign_extender
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu_tb.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module asu
|
|
-- Compiling module lu
|
|
-- Compiling module alu
|
|
-- Compiling module alu_tb
|
|
|
|
Top level modules:
|
|
alu_tb
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_counter.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module instruction_counter
|
|
|
|
Top level modules:
|
|
instruction_counter
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/ByteIM.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module rom
|
|
-- Compiling module ByteIM
|
|
|
|
Top level modules:
|
|
rom
|
|
ByteIM
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/alu.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module asu
|
|
-- Compiling module lu
|
|
-- Compiling module alu
|
|
|
|
Top level modules:
|
|
alu
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/seven_seg_4digit.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module seven_seg
|
|
-- Compiling module seven_seg_4digit
|
|
|
|
Top level modules:
|
|
seven_seg_4digit
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/instruction_classifier_tb.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module instruction_classifier
|
|
-- Compiling module instruction_classifier_tb
|
|
|
|
Top level modules:
|
|
instruction_classifier_tb
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/assignment3.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module rom
|
|
-- Compiling module ram
|
|
-- Compiling module register_file
|
|
-- Compiling module instruction_counter
|
|
-- Compiling module instruction_classifier
|
|
-- Compiling module control_unit
|
|
-- Compiling module asu
|
|
-- Compiling module lu
|
|
-- Compiling module alu
|
|
-- Compiling module shifter
|
|
-- Compiling module sign_extender
|
|
-- Compiling module gatereg
|
|
-- Compiling module assignment3
|
|
|
|
Top level modules:
|
|
shifter
|
|
assignment3
|
|
|
|
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/register_file.sv
|
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
|
-- Compiling module register_file
|
|
|
|
Top level modules:
|
|
register_file
|
|
|
|
} {} {}}
|