riley
fe53955748
Added mem[0x000] to log message when printing registers. Replaced 8 delay with explicit 5x 2 delays. (NOTE: Needed an extra one for ensuring write-back when comparing results. Fixed bug where the wrong registers were being added together when creating the comparison point in the testbench. Fixed testbench bug where S4 was checked twice and S5 not checked at all. Updated display message on test failure to reflect that it is the pipelined version, not the single-cycle.
137 lines
4.4 KiB
Systemverilog
137 lines
4.4 KiB
Systemverilog
`include "assignment3.sv"
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`timescale 1us/10ns
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`define PRINT_REGISTERS(regs)\
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$display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\tmem[0] = 0x%0x\n",\
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regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15], \
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regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23], \
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CPU.RAM.mem[0]\
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);
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`define TEST_CHECK(cond) if (cond) begin end else begin \
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$display("Check %s failed", `"cond`"); \
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`PRINT_REGISTERS(CPU.REGS.regs); \
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num_errors += 1; \
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end
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module mips_pipelined_tb();
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logic [0:0] clk;
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logic [0:0] rst;
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assignment3 CPU (clk, rst);
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initial clk = 0;
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initial rst = 0;
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always #1 clk = ~clk;
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integer num_errors = 0;
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initial begin
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rst = 1;
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#2;
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rst = 0;
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#2;
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$dumpfile("output.vcd");
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$dumpvars(0, clk);
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$dumpvars(1, CPU.REGS);
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$dumpvars(2, CPU.ROM);
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$dumpvars(3, CPU.RAM);
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$dumpvars(4, CPU.PC);
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$dumpvars(5, CPU.CONTROL_UNIT);
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$dumpvars(6, CPU.ALU);
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$display("Beginning Pipelined MIPS tests");
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#2; // 4x steps to allow pipeline to fill up
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#2;
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#2;
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#2;
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#2;
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`TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[9] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[10] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[9] == 32'd7);
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#2;
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`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
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#2;
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`TEST_CHECK(CPU.RAM.mem[0] == 32'd7);
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#2;
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`TEST_CHECK(CPU.REGS.regs[10] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
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#2;
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`TEST_CHECK(CPU.REGS.regs[11] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[13] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]) );
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`TEST_CHECK(CPU.REGS.regs[11] == 32'd14);
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#2;
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`TEST_CHECK(CPU.REGS.regs[12] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[13] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[14] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
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`TEST_CHECK(CPU.REGS.regs[12] == -32'sd7);
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#2;
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`TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3) );
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`TEST_CHECK(CPU.REGS.regs[13] == 32'd10);
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#2;
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`TEST_CHECK(CPU.REGS.regs[14] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[15] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[16] == 32'd0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));
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`TEST_CHECK(CPU.REGS.regs[14] == 32'd3);
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#2;
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`TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
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`TEST_CHECK(CPU.REGS.regs[16] == 32'd2);
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#2;
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`TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
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`TEST_CHECK(CPU.REGS.regs[17] == 32'd15);
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#2;
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`TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
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`TEST_CHECK(CPU.REGS.regs[18] == 32'd13);
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#2;
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`TEST_CHECK(CPU.REGS.regs[19] == ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]));
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`TEST_CHECK(CPU.REGS.regs[19] == 32'hfffffff0);
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#2;
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`TEST_CHECK(CPU.REGS.regs[20] == ( $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]) ));
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`TEST_CHECK(CPU.REGS.regs[20] == 32'd1);
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#2;
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`TEST_CHECK(CPU.REGS.regs[21] == ( CPU.REGS.regs[12] < CPU.REGS.regs[14] ));
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`TEST_CHECK(CPU.REGS.regs[21] == 32'd0);
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// TODO: Verify program never branches
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#2;
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#2;
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#2;
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#2;
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// TODO: Verify final program register state
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if (num_errors == 0) begin $display("\x1b[38;5;10mAll pipelined MIPS tests passing\x1b[m");
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end else begin $display("\x1b[38;5;9m%0d pipelined MIPS test(s) failing\x1b[m", num_errors); end
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$dumpflush;
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$finish;
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end
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endmodule |