TroubleElectrical
d2ba06b255
Also have a placeholder MUX to place before the ALU for adding hazard unit functionality
80 lines
2.3 KiB
Systemverilog
80 lines
2.3 KiB
Systemverilog
`ifndef HAZARD_SV
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`define HAZARD_SV
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module hazard_unit (
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// (I)Decode/EXecute stage
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input logic idex_MemRead,
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input logic [4:0] idex_Rt,
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input logic [4:0] idex_Rs,
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// EXecute/MEMory stage
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input logic exmem_RegWrite,
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input logic [4:0] exmem_Rd,
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// MEMory/WriteBack stage
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input logic memwb_RegWrite,
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input logic [4:0] memwb_Rd,
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// (I)Fetch/(I)Decode stage
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input logic [4:0] ifid_Rs,
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input logic [4:0] ifid_Rt,
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// branch / jump control
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input logic branch_taken,
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input logic jump_taken,
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// outputs
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output logic [1:0] forwardA,
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output logic [1:0] forwardB,
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output logic stallF, // Stall OC register
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output logic stallD, // Stall Instruction Memory
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output logic flushE, // Flush ALU inputs
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output logic flushD // Flush
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);
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// Forwarding for A/B ALU inputs
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// 00 = no forwarding
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// 01 = forward from MEM/WB
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// 10 = forward from EX/MEM
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always_comb begin
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// defaults
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forwardA = 2'b00;
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forwardB = 2'b00;
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stallF = 1'b0;
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stallD = 1'b0;
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flushE = 1'b0;
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flushD = 1'b0;
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// Forwarding for ALU src A
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if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rs))
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forwardA = 2'b10;
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else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rs))
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forwardA = 2'b01;
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// Forwarding for ALU src B
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if (exmem_RegWrite && (exmem_Rd != 5'd0) && (exmem_Rd == idex_Rt))
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forwardB = 2'b10;
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else if (memwb_RegWrite && (memwb_Rd != 5'd0) && (memwb_Rd == idex_Rt))
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forwardB = 2'b01;
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// Load-use hazard stall
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// if instruction in EX is a load and next instruction uses its result
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if (idex_MemRead &&
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((idex_Rt == ifid_Rs) || (idex_Rt == ifid_Rt))) begin
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stallF = 1'b1;
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stallD = 1'b1;
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flushE = 1'b1; // insert bubble into EX
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end
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// Control hazard flush
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// branch/jump resolved in EX
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if (branch_taken || jump_taken) begin
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flushD = 1'b1; // flush wrong instruction in decode
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flushE = 1'b1; // flush wrong instruction in execute
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end
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end
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endmodule
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`endif
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