Added Byte addressable ROM from Slides

Quartus/A1_Q1/db/seven_seg.tmw_info

@@ -0,0 +1,4 @@
+start_full_compilation:s
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation

modules/ByteIM.sv

@@ -0,0 +1,14 @@
+`include "rom.sv"
+
+module ByteIM #(parameter m=5,n=2) (
+    input logic [m-1:0] Ad,
+    output logic [(2**n)*8-1:0] Dout );
+
+    // 2**n byte wide words
+    // m bit wide byte address
+    // 2**m bytes of memory
+    // 2**(m-n) memory words
+    // 2**(n+3) bit wide words
+    // Reads the whole word that contains the addressed byte
+    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
+endmodule

modules/alu.sv

@@ -3,31 +3,19 @@
 
 `include "asu.sv"
 `include "lu.sv"
-`include "seven_seg.sv"
 
 // flags[0:0] = Cout
 // flags[1:1] = Overflow
 module alu #(parameter width=2)(input logic [3:0] op,
     input logic [2**width-1:0] A, input logic [2**width-1:0] B,
     output logic [2**width-1:0] OUT_1, output logic[1:0] flags
-`ifdef SYNTHESIS
-	, output logic [7:0] out_seg1);
-`else
     );
-`endif
     // intermediate logic for handling asu output
     logic [0:0] asu_op;
     logic [2**width-1:0] asu_out;
     logic [1:0] asu_flags;
-    logic [7:0] asu_seven_seg_out;
 
-    // NOTE: For demo only
-    // TODO: Strip this for assignment 2
-    `ifdef SYNTHESIS
-        asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1], asu_seven_seg_out);
-    `else
     asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
-    `endif
 
     logic [2**width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
@@ -47,11 +35,5 @@ module alu #(parameter width=2)(input logic [3:0] op,
             default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
     end
-
-    // NOTE: For demo only
-    // TODO: Strip this for assignment 2
-    `ifdef SYNTHESIS
-	    seven_seg dut(OUT_1, 1'b1, out_seg1);
-    `endif
 endmodule
 `endif

modules/asu.sv

@@ -1,20 +1,14 @@
 `ifndef ASU_H_SV
 `define ASU_H_SV
 
-`include "seven_seg.sv"
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
     output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
-// Used to switch between demo mode and testbench mode
-// TODO: Strip for assignment 2
-`ifdef SYNTHESIS
-	, output logic[7:0] out_seg_1);
-`else
     );
-`endif
 
     logic [2**width-1:0] operand;
+
     always_comb begin
         // A + (sub) ? B : -B
         // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
@@ -27,10 +21,5 @@ module asu #(parameter width = 2)(
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
 
-	// Include seven segment visual output for hardware builds only
-    // TODO: Strip this for assignment 2 outright
-    `ifdef SYNTHESIS 
-	    seven_seg dut(OUT_1, 1'b1, out_seg_1);
-    `endif
 endmodule
 `endif

modules/rom.sv

@@ -0,0 +1,15 @@
+
+module ROM #(parameter m=7,p=4) (
+        input logic [m-1:0] Ad,
+        output logic [p-1:0] Dout
+    );
+    
+    logic [p-1:0] mem[2**m-1:0];
+    assign Dout = mem[Ad];
+
+    //Load the program in memory
+    // The machine code stored in text file program.dat written in Hex format
+    initial begin
+        $readmemh("program.dat",mem); //$readmemb for binary
+    end
+endmodule // end ROM module