Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable

modules/asu.sv

@@ -7,11 +7,11 @@ module asu #(parameter width = 2)(
     always_comb begin
         // A + (sub) ? B : -B
         // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
-        operand = (B ^ {(width){op}});
-        {COUT, OUT_1} = A + operand + {{(width-1){1'b0}}, op};
+        operand = (B ^ {(2**width){op}});
+        {COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
     end
 
     // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
-    // Cin for width-2'th bit to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
-    assign OUT_CIN = A[width-1] ^ operand[width-1] ^ OUT_1[width-1];
+    // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
+    assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
 endmodule

modules/instruction_classifier.sv

@@ -1,8 +1,9 @@
-module instruction_classifier(input logic op[5:0],
+module instruction_classifier(input logic[5:0] op,
     output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
     output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,
     output logic[0:0] M);
 
+    always_comb begin
         logic [6:0] OUT_1;
         casez (op)
             6'b1?????: OUT_1 = 7'b1000000;
@@ -14,12 +15,12 @@ module instruction_classifier(input logic op[5:0],
             6'b000000: OUT_1 = 7'b0000001;
         endcase
 
-    assign R  = OUT_1[6];
-    assign B1 = OUT_1[5];
-    assign J  = OUT_1[4];
-    assign B2 = OUT_1[3];
-    assign I  = OUT_1[2];
-    assign F  = OUT_1[1];
-    assign M  = OUT_1[0];
-
+        R  = OUT_1[6];
+        B1 = OUT_1[5];
+        J  = OUT_1[4];
+        B2 = OUT_1[3];
+        I  = OUT_1[2];
+        F  = OUT_1[1];
+        M  = OUT_1[0];
+    end
 endmodule

modules/shifter.sv

@@ -1,12 +1,15 @@
-module shifter #(width=8)(input logic op[1:0],
-    input logic[width-1:0] A, input logic[width-1:0] B,
+module shifter #(width=8)(input logic [2:0] op,
+    input logic[width-1:0] A, input logic[width-1:0] C, input logic[$clog2(width)-1:0] B,
     output logic[width-1:0] OUT_1);
 
     always_comb begin
         case (op)
-            00: OUT_1 = A << B;
-            01: OUT_1 = A >> B;
-            10: OUT_1 = $signed(A) >>> B;
+            3'b000: OUT_1 = A << C;
+            3'b001: OUT_1 = A >> C;
+            3'b011: OUT_1 = $signed(A) >>> C;
+            3'b100: OUT_1 = A << B;
+            3'b101: OUT_1 = A >> B;
+            3'b111: OUT_1 = $signed(A) >>> B;
             default:;
         endcase
     end    

tests/asu_tb.sv

@@ -11,9 +11,7 @@ module asu_tb #(width=8)();
     logic [0:0] Cout_exp;
     logic [0:0] Cin_exp;   // TODO
 
-    logic [0:0] Signed_overflow;
-
-    asu #(width) dut(op, A, B, C, Cout, Cin);
+    asu #($clog2(width)) dut(op, A, B, C, Cout, Cin);
 
     integer error_count;
     initial begin

tests/instruction_classifier_tb.sv

@@ -1 +1,52 @@
-`#include "instruction_classifier.sv"
+`include "instruction_classifier.sv"
+module instruction_classifier_tb();
+    logic [5:0] op;
+    logic [6:0] C;
+    logic [5:0] ops[12];
+    logic [6:0] C_exp[12];
+
+    instruction_classifier dut(op, C[0:0], C[1:1], C[2:2], C[3:3], C[4:4], C[5:5], C[6:6]);
+
+    integer error_count;
+    initial begin
+        ops[0] = 6'b000000;
+        C_exp[0] = 7'b1000000;
+        ops[1] = 6'b000001;
+        C_exp[1] = 7'b0100000;
+        ops[2] = 6'b000010;
+        C_exp[2] = 7'b0010000;
+        ops[3] = 6'b000100;
+        C_exp[3] = 7'b0001000;
+        ops[4] = 6'b001000;
+        C_exp[4] = 7'b0000100;
+        ops[5] = 6'b010000;
+        C_exp[5] = 7'b0000010;
+        ops[6] = 6'b100000;
+        C_exp[6] = 7'b0000001;
+
+        ops[7] = 6'b000011;
+        C_exp[7] = 7'b0010000;
+        ops[8] = 6'b000101;
+        C_exp[8] = 7'b0001000;
+        ops[9] = 6'b001001;
+        C_exp[9] = 7'b0000100;
+        ops[10] = 6'b010001;
+        C_exp[10] = 7'b0000010;
+        ops[11] = 6'b100001;
+        C_exp[11] = 7'b0000001;
+
+        error_count = 0;
+        $display("Beginning Instruction Classifier tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            #1;
+            if (C != C_exp[N]) begin
+                $display("\t\x1b[38;5;9mInstruction 0b%b produced 0b%b but 0b%b was expected\x1b[m", op, C, C_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll Instruction Classifier tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d Instruction Classifier test(s) failing\x1b[m", error_count);
+    end
+
+endmodule

tests/lu_tb.sv

@@ -7,30 +7,30 @@ module lu_tb #(parameter W=4)();
     logic [W-1:0] C;
     logic [W-1:0] C_exp[16];
 
-    lu #(W/2) dut();
+    lu #(W/2) dut(op, A, B, C);
 
     integer error_count;
     initial begin
         // AND
-        C_exp[0]  = {W{1'b0}};
-        C_exp[1]  = {W{1'b0}};
-        C_exp[2]  = {W{1'b0}};
-        C_exp[3]  = {W{1'b0}};
+        C_exp[0]  = {{W{1'b0}}, {1'b0}};
+        C_exp[1]  = {{W{1'b0}}, {1'b0}};
+        C_exp[2]  = {{W{1'b0}}, {1'b0}};
+        C_exp[3]  = {{W{1'b0}}, {1'b1}};
         // OR
-        C_exp[4]  = {W{1'b0}};
-        C_exp[5]  = {W{1'b1}};
-        C_exp[6]  = {W{1'b1}};
-        C_exp[7]  = {W{1'b1}};
+        C_exp[4]  = {{W{1'b0}}, {1'b0}};
+        C_exp[5]  = {{W{1'b0}}, {1'b1}};
+        C_exp[6]  = {{W{1'b0}}, {1'b1}};
+        C_exp[7]  = {{W{1'b0}}, {1'b1}};
         // XOR
-        C_exp[8]  = {W{1'b0}};
-        C_exp[9]  = {W{1'b1}};
-        C_exp[10] = {W{1'b1}};
-        C_exp[11] = {W{1'b0}};
+        C_exp[8]  = {{W{1'b0}}, {1'b0}};
+        C_exp[9]  = {{W{1'b0}}, {1'b1}};
+        C_exp[10] = {{W{1'b0}}, {1'b1}};
+        C_exp[11] = {{W{1'b0}}, {1'b0}};
         // NOR
-        C_exp[12] = {W{1'b1}};
-        C_exp[13] = {W{1'b0}};
-        C_exp[14] = {W{1'b0}};
-        C_exp[15] = {W{1'b0}};
+        C_exp[12] = {{W{1'b1}}, {1'b1}};
+        C_exp[13] = {{W{1'b1}}, {1'b0}};
+        C_exp[14] = {{W{1'b1}}, {1'b0}};
+        C_exp[15] = {{W{1'b1}}, {1'b0}};
 
         error_count = 0;
         op = 0;
@@ -42,12 +42,13 @@ module lu_tb #(parameter W=4)();
                 for (integer K = 0; K < 2; ++K) begin
                     #1;
                     if (C != C_exp[N*2*2 + M*2 + K]) begin
-                        $display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", op, A, B, C, C_exp[N*2*2 + M*2 + K]);
+                        $display("\t\x1b[38;5;9mLU(%0d) Op 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N*2*2+M*2+K, op, A, B, C, C_exp[N*2*2 + M*2 + K]);
                         error_count = error_count + 1;
                     end
                     B = 1;
                 end
                 A = 1;
+                B = 0;
             end
             A = 0;
             B = 0;

tests/shifter_tb.sv

@@ -1,5 +1,77 @@
-`#include "shifter.sv"
-
+`include "shifter.sv"
 module shifter_tb #(width=8)();
+    logic [2:0] op;
+    logic [width-1:0] Y;
+    logic [width-1:0] A_in;
+    logic [$clog2(width)-1:0] B_in;
+    logic [width-1:0] C_in;
 
+    logic [2:0] ops[6];
+    logic [width-1:0] A[6];
+    logic [$clog2(width)-1:0] B[6];
+    logic [width-1:0] C[6];
+    logic [width-1:0] Y_exp[6];
+
+    shifter #(width) dut(op, A_in,C_in,B_in,Y);
+
+    integer error_count;
+    initial begin
+        // Test left shift by C
+        ops[0] = 3'b000;
+        A[0] = {{(width-1){1'b0}}, {1'b1}};
+        C[0] = {{(width-1){1'b0}}, {1'b1}};
+        B[0] = {width{1'b0}};
+        Y_exp[0] = {{(width-2){1'b0}}, {2'b10}};
+
+        // Test left shift by B
+        ops[1] = 3'b100;
+        A[1] = {{(width-1){1'b0}}, {1'b1}};
+        C[1] = {{(width-1){1'b0}}, {1'b1}};
+        B[1] = {{($clog2(width)-2){1'b0}}, 2'b10};
+        Y_exp[1] = {{(width-3){1'b0}}, {3'b100}};
+
+        // Test Logical right shift by C
+        ops[2] = 3'b001;
+        A[2] = {{(width-2){1'b0}}, {2'b10}};
+        C[2] = {{(width-1){1'b0}}, {1'b1}};
+        B[2] = {width{1'b0}};
+        Y_exp[2] = {{(width-1){1'b0}}, {1'b1}};
+
+        // Test Logical right shift by B
+        ops[3] = 3'b101;
+        A[3] = {{(width-1){1'b0}}, {2'b10}};
+        C[3] = {{(width-1){1'b0}}, {1'b1}};
+        B[3] = {{($clog2(width)-2){1'b0}}, 2'b10};
+        Y_exp[3] = {{(width-1){1'b0}}, {1'b0}};
+
+        // Test arithmetic shift right by C
+        ops[4] = 3'b011;
+        A[4] = {{(width-1){1'b1}}, 1'b0};   // -2
+        C[4] = {{(width-1){1'b0}}, 1'b1};   // 1
+        B[4] = {{(width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[4] = {width{1'b1}};           // -1
+
+        // Test arithmetic shift right by B
+        ops[5] = 3'b111;
+        A[5] = {{(width-2){1'b1}}, 2'b00};   // -4
+        C[5] = {{(width-1){1'b0}}, 1'b1};   // 1
+        B[5] = {{(width-2){1'b0}}, 2'b10};  // 2
+        Y_exp[5] = {width{1'b1}};           // -1
+
+        error_count = 0;
+        $display("Beginning Shifter tests");
+        for (integer N = 0; N < $size(ops); ++N) begin
+            op = ops[N];
+            A_in = A[N];
+            B_in = B[N];
+            C_in = C[N];
+            #1;
+            if (Y != Y_exp[N]) begin
+                $display("\t\x1b[38;5;9mShifter(%0d) Op 0b%b(0b%b, 0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N, op, A_in, B_in, C_in, Y, Y_exp[N]);
+                error_count = error_count + 1;
+            end
+        end
+        if (error_count == 0) $display("\x1b[38;5;10mAll Shifter tests passing\x1b[m");
+        else $display("\x1b[38;5;9m%0d Shifter test(s) failing\x1b[m", error_count);
+    end
 endmodule

tests/tests.sv

@@ -1,3 +1,5 @@
 `include "tests/seven_seg_tb.sv"
 `include "tests/lu_tb.sv"
 `include "tests/asu_tb.sv"
+`include "tests/instruction_classifier_tb.sv"
+`include "tests/shifter_tb.sv"