3 Commits

Include renames

Author	SHA1	Message	Date
TroubleElectrical	5d9e7f541e	Updated RAM code to make sure Bus width is 32 bits	2026-10-16 11:32:47 +11:00
TroubleElectrical	dc32347c9b	Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)	2026-09-09 14:27:11 +10:00
TroubleElectrical	60e5dae43b	Added ModelSim folder (and have to add files into it as to allow for different testbench code)	2026-09-08 16:32:01 +10:00