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TroubleElectrical/FPGA_Uni
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Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
135 Commits 2 Branches 0 Tags
de1f346f64db3d617e4afe37232c65f1fdc5e27e
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3 Commits
Author SHA1 Message Date
TroubleElectrical 9e5fb6f52b Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board 2026-09-15 16:52:48 +10:00
TroubleElectrical 60e5dae43b Added ModelSim folder (and have to add files into it as to allow for different testbench code) 2026-09-08 16:32:01 +10:00
TroubleElectrical 2208eb4f16 Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board. 2026-09-08 15:36:51 +10:00
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