5 Commits

Include renames

Author	SHA1	Message	Date
riley	d9f44f93df	Halfway added imm,branch and mem ops	2026-10-15 14:46:51 +11:00
riley	a04d6b92cb	Updated register file to use 2^n rather than n	2026-10-13 12:43:53 +11:00
riley	979f12b692	Added zero initialization for r0	2026-10-12 21:29:07 +11:00
TroubleElectrical	b49e294b7d	Updated register_file.sv with proper naming scheme and 32bit width	2026-10-08 15:10:40 +11:00
riley	0ef2aeeb48	Added instruction counter and register file	2026-10-08 14:13:38 +11:00