22 lines
661 B
Systemverilog
22 lines
661 B
Systemverilog
`ifndef REGISTER_FILE_H
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`define REGISTER_FILE_H
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module register_file #(parameter width=5, parameter nregs=16)(
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input logic [0:0] clk, input logic[0:0] we,
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input logic [$clog(nregs)-1:0] A_W1, input logic [2**width-1:0] W1,
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input logic [$clog(nregs)-1:0] A_R1, output logic [2**width-1:0] R1,
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input logic [$clog(nregs)-1:0] A_R2, output logic [2**width-1:0] R2
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);
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localparam BW = 2**width;
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logic [2**width-1:0] regs[nregs];
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always_ff @(posedge clk) begin
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if (we & (A_W1 != {(2**width){1'b0}} )) begin
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regs[A_W1] <= W1;
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end
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end
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assign R1 = regs[A_R1];
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assign R2 = regs[A_R2];
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endmodule
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`endif |