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TroubleElectrical/FPGA_Uni
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Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
43 Commits 2 Branches 0 Tags
900b544bc69664991a9cc19a9d4eb92a20f0c2e9
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3 Commits
Author SHA1 Message Date
TroubleElectrical 9e5fb6f52b Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board 2026-09-15 16:52:48 +10:00
TroubleElectrical 05361dcf70 Added all Testbenches to Modelsim and confirmed working operation 2026-09-15 15:15:00 +10:00
TroubleElectrical dc32347c9b Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3) 2026-09-09 14:27:11 +10:00
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