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TroubleElectrical
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FPGA_Uni
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8675f5b8ee727ca6d40561ac07853fece54147e3
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3 Commits
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TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
TroubleElectrical
dc32347c9b
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00
TroubleElectrical
32eea036a8
Added projects for A1 q2 to q6
2026-09-04 13:12:33 +10:00