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FPGA_Uni
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7d489ab77c6bed83abd747fd3ef770d5cd54acf9
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3 Commits
Include renames
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TroubleElectrical
60e5dae43b
Added ModelSim folder (and have to add files into it as to allow for different testbench code)
2026-09-08 16:32:01 +10:00
TroubleElectrical
2208eb4f16
Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board.
2026-09-08 15:36:51 +10:00
TroubleElectrical
32eea036a8
Added projects for A1 q2 to q6
2026-09-04 13:12:33 +10:00