Logo
Explore Help
Sign In
TroubleElectrical/FPGA_Uni
Watch 1
Star 0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
28 Commits 2 Branches 0 Tags
78efccfe1e389d718e9b8a8c44227d99a0ead578
Commit Graph
2 Commits
Author SHA1 Message Date
TroubleElectrical a73990b242 Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2) 2026-09-10 15:24:44 +10:00
TroubleElectrical dc32347c9b Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3) 2026-09-09 14:27:11 +10:00
Powered by Gitea Version: 28.3.0 Page: 29ms Template: 4ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API