TroubleElectrical/FPGA_Uni
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5 Commits
Author SHA1 Message Date
riley 92a0cb17da Updated assignment 2 to reflect prior changes. Fixed instruction ordering for register file module (again). Fixed typo that limited the space the ALU could write its flags out to. Swapped ordering to be correct when determining if we are storing the result from ALU or MEM. 
Added a QUARTUS_SYNTH around the display logic at the end of the module.
Partially fixed control_unit module, still seems to need some changes as branching doesn't appear to work at all.
 2026-10-16 11:38:35 +11:00
riley a63d46bc77 Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni 2026-10-15 15:54:38 +11:00
riley 04d1d3e2fe Added control unit. TODO: Test 2026-10-15 15:53:59 +11:00
TroubleElectrical cd7fecd1c4 Updated code such that it will compile 2026-10-15 15:32:15 +11:00
riley a336df9d80 Reworked CPU to use control unit 2026-10-15 15:16:57 +11:00