7 Commits

Include renames

Author	SHA1	Message	Date
riley	19cd7ac177	Updated ALU and ASU modules to conditionally require seven-segment output logic. Used for the assignment 1 demo and MUST be stripped for assignment 2.	2026-09-15 21:27:04 +10:00
TroubleElectrical	9e5fb6f52b	Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board	2026-09-15 16:52:48 +10:00
riley	c4ebde7692	Updated ASU to use an explicit MUX rather than the XOR inversion 'trick' when calculating the operand	2026-09-14 00:13:17 +10:00
riley	19ba1bf473	Added header guards to prevent errors from double-inclusions	2026-09-13 23:09:08 +10:00
riley	5acf1c8b87	Fixed bug in adder/subtracter where code assuming width was the bit width was not updated when moving to the 2**N approach required by the assignment. Updated adder/subtracter testbench to correctly instantiate the asser/subtracter and removed unused variable	2026-09-08 22:49:22 +10:00
TroubleElectrical	60e5dae43b	Added ModelSim folder (and have to add files into it as to allow for different testbench code)	2026-09-08 16:32:01 +10:00
riley	6668969b03	Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v	2026-09-03 16:05:52 +10:00