 riley
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9794f26137
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Fixed error in logic unit testbench where it didn't instansiate the DUT at all as well as some faulty test cases and reset logic
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2026-09-08 22:00:07 +10:00 |
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 TroubleElectrical
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60e5dae43b
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Added ModelSim folder (and have to add files into it as to allow for different testbench code)
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2026-09-08 16:32:01 +10:00 |
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riley
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a89a66d34d
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Fixed bug where includes still refered to verilog rather than systemverilog. Inverted test cases in seven segment test bench to reflect changes made to module. There is still a bug with the module where it outputs garbage
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2026-09-03 16:32:56 +10:00 |
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riley
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6668969b03
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Made it clear that we are using SystemVerilog by renaming HDL files to end in .sv rather than .v
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2026-09-03 16:05:52 +10:00 |
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