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TroubleElectrical
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FPGA_Uni
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559ff01d69c7b36c4c4fcd9ef5ece7b89fa091ed
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3 Commits
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TroubleElectrical
9e5fb6f52b
Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
2026-09-15 16:52:48 +10:00
TroubleElectrical
05361dcf70
Added all Testbenches to Modelsim and confirmed working operation
2026-09-15 15:15:00 +10:00
TroubleElectrical
dc32347c9b
Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
2026-09-09 14:27:11 +10:00