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TroubleElectrical/FPGA_Uni
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Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
30 Commits 2 Branches 0 Tags
49f539c855c1b235b6222dd5c66ad22c358f57cb
Commit Graph
7 Commits
Author SHA1 Message Date
TroubleElectrical a73990b242 Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2) 2026-09-10 15:24:44 +10:00
TroubleElectrical dc32347c9b Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3) 2026-09-09 14:27:11 +10:00
TroubleElectrical 60e5dae43b Added ModelSim folder (and have to add files into it as to allow for different testbench code) 2026-09-08 16:32:01 +10:00
TroubleElectrical 2208eb4f16 Updated Q2 project and LU code such that it operates properly on the board. Changed to utilising a case statement for easier readability and also compiled and tested the code on the board. 2026-09-08 15:36:51 +10:00
TroubleElectrical 32eea036a8 Added projects for A1 q2 to q6 2026-09-04 13:12:33 +10:00
TroubleElectrical 3114cd6b80 Added the updated A1_Q1 Quartus compilation 2026-09-03 19:22:52 +10:00
TroubleElectrical 31a4496904 Including quartus prime lite edition project folders for flashing the project to the board 2026-09-03 16:34:31 +10:00
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