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TroubleElectrical/FPGA_Uni
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76 Commits 2 Branches 0 Tags
353923eadf31eb1b895f061cc6d6679e28da96e8
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4 Commits
Author SHA1 Message Date
TroubleElectrical e57e8f362a Updated assignment 2 dependency modules (currently 8 errors in compile) 2026-10-13 12:23:52 +11:00
riley 1faa7fc3f0 Updated ram and rom modules so that naming is more consistent 2026-10-12 11:49:35 +11:00
riley 102d5b4b7a Updated RAM interface to be more inline with ROM interface 2026-10-08 14:56:52 +11:00
riley ab561dd510 Implemented RAM. Possible issue by using async assignments in initial begin. 2026-10-08 14:55:28 +11:00
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