 TroubleElectrical
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5d9e7f541e
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Updated RAM code to make sure Bus width is 32 bits
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2026-10-16 11:32:47 +11:00 |
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TroubleElectrical
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9e5fb6f52b
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Updated ASU (Q3) to utilise the 7seg for output, confirmed operation of Q1 to Q3 on board
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2026-09-15 16:52:48 +10:00 |
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TroubleElectrical
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05361dcf70
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Added all Testbenches to Modelsim and confirmed working operation
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2026-09-15 15:15:00 +10:00 |
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TroubleElectrical
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a73990b242
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Added ASU (Q3) testbench to the modelsim projects folder (also confirmed operation of q2)
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2026-09-10 15:24:44 +10:00 |
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TroubleElectrical
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dc32347c9b
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Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
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2026-09-09 14:27:11 +10:00 |
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TroubleElectrical
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60e5dae43b
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Added ModelSim folder (and have to add files into it as to allow for different testbench code)
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2026-09-08 16:32:01 +10:00 |
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