6 Commits

Include renames

Author	SHA1	Message	Date
riley	fe53955748	Fixed bug in test code where there was a hazzard, despite testing assuming no hazzard. Updated testbench to reflect this (Ln57-62). ... Added mem[0x000] to log message when printing registers. Replaced 8 delay with explicit 5x 2 delays. (NOTE: Needed an extra one for ensuring write-back when comparing results. Fixed bug where the wrong registers were being added together when creating the comparison point in the testbench. Fixed testbench bug where S4 was checked twice and S5 not checked at all. Updated display message on test failure to reflect that it is the pipelined version, not the single-cycle.	2026-11-05 16:15:06 +11:00
riley	ef6bd3aec9	Added test assemblies for assignment 3 / pipelining	2026-11-04 15:42:22 +11:00
riley	973b9260b6	Fixed (maybe bug) in demo program where program branches back to prior instruction.	2026-10-20 16:21:55 +11:00
riley	4c7e2ff085	Fixed instruction width issue in ROM. Stripped all comments to form minimal HEX file to rule out possible parser issues.	2026-10-16 11:29:04 +11:00
riley	76cd7931b6	Realized that, while the assembled is not binary, it is still loadable by verilog.	2026-10-08 14:18:11 +11:00
riley	aab18425f9	Added test assembly code	2026-10-08 14:08:35 +11:00