Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es

modules/instruction_classifier.sv

@@ -1,3 +1,4 @@
+// TODO: This needs to be reworked to use manual mux-ing as to ensure low gate delay
 module instruction_classifier(input logic[5:0] op,
     output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J,
     output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,