From cd7074a78cd3616fac864920b8186c3b73ea39c5 Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Thu, 10 Sep 2026 15:56:59 +1000 Subject: [PATCH] Need to change instruction classifier implementation to use a more parallel architecture as case statements can produce sequential MUX'es --- modules/instruction_classifier.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/instruction_classifier.sv b/modules/instruction_classifier.sv index e0a31f7..4e43c0c 100644 --- a/modules/instruction_classifier.sv +++ b/modules/instruction_classifier.sv @@ -1,3 +1,4 @@ +// TODO: This needs to be reworked to use manual mux-ing as to ensure low gate delay module instruction_classifier(input logic[5:0] op, output logic[0:0] R, output logic[0:0] B1, output logic[0:0] J, output logic[0:0] B2, output logic[0:0] I, output logic[0:0] F,