Fixed ByteIM.sv and removed seven seg from A3 code

modules/assignment3.sv

@@ -11,25 +11,12 @@
 `include "sign_extender.sv"
 `include "gatereg.sv"
 
-`ifdef QUARTUS_SYNTH
-`include "seven_seg_4digit.sv"
-`endif
 
 module assignment3 #(width=5, romsz=9, ramsz=10)(
     input logic [0:0] clk, input logic [0:0] rst
-`ifdef QUARTUS_SYNTH
-    ,
-	input logic [4:0] HID_Register,
-	input logic [0:0] HID_PC,
-	input logic [0:0] HID_Hi_Low,
-	
-	output logic[7:0] out_seg_0,
-	output logic[7:0] out_seg_1,
-	output logic[7:0] out_seg_2,
-	output logic[7:0] out_seg_3
-`endif
 );
-	logic [31:0] regs_out [32];
+	
+    logic [31:0] regs_out [32];
 
 	logic [2**width-1:0] pc_addr, pc_addr_2;
 	logic [2**width-1:0] pc_addr_write;
@@ -108,4 +95,4 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
 	gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
 	assign rd_mem = mem_out_1;
 endmodule
-`endif
+`endif