diff --git a/modules/ByteIM.sv b/modules/ByteIM.sv
index 6e913a7..ef70d34 100644
--- a/modules/ByteIM.sv
+++ b/modules/ByteIM.sv
@@ -10,5 +10,5 @@ module ByteIM #(parameter m=5,n=2) (
     // 2**(m-n) memory words
     // 2**(n+3) bit wide words
     // Reads the whole word that contains the addressed byte
-    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
+    ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout);
 endmodule
diff --git a/modules/assignment3.sv b/modules/assignment3.sv
index 59bf42f..116b6be 100644
--- a/modules/assignment3.sv
+++ b/modules/assignment3.sv
@@ -11,25 +11,12 @@
 `include "sign_extender.sv"
 `include "gatereg.sv"
 
-`ifdef QUARTUS_SYNTH
-`include "seven_seg_4digit.sv"
-`endif
 
 module assignment3 #(width=5, romsz=9, ramsz=10)(
     input logic [0:0] clk, input logic [0:0] rst
-`ifdef QUARTUS_SYNTH
-    ,
-	input logic [4:0] HID_Register,
-	input logic [0:0] HID_PC,
-	input logic [0:0] HID_Hi_Low,
-	
-	output logic[7:0] out_seg_0,
-	output logic[7:0] out_seg_1,
-	output logic[7:0] out_seg_2,
-	output logic[7:0] out_seg_3
-`endif
 );
-	logic [31:0] regs_out [32];
+	
+    logic [31:0] regs_out [32];
 
 	logic [2**width-1:0] pc_addr, pc_addr_2;
 	logic [2**width-1:0] pc_addr_write;
@@ -108,4 +95,4 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
 	gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);
 	assign rd_mem = mem_out_1;
 endmodule
-`endif
\ No newline at end of file
+`endif