An attempt was made to fix errors with this. There is an issue with either branching and/or register dependencies

modules/gatereg.sv

@@ -5,7 +5,7 @@ module gatereg #(width, ndelay=1)(
     logic [2**width-1:0] hold_value[ndelay];
 
     assign out = hold_value[ndelay-1];
-    always_ff @( posedge clk ) begin
+    always_ff @( posedge clk or posedge rst) begin
         if (rst) begin
             for (integer i = 0; i < ndelay; ++i) begin
                 hold_value[i] <= {(2**width){1'b0}};