An attempt was made to fix errors with this. There is an issue with either branching and/or register dependencies

modules/assignment3.sv

@@ -20,7 +20,6 @@ module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=
 	// Inputs
 	logic [0:0] hazard_m2r_1, hazard_m2r_2;
 	logic [0:0] hazard_reg_we_1, hazard_reg_we_2, hazard_reg_we_3;
-	logic [0:0] hazard_branch_taken, hazard_jump_taken;
 	logic [4:0] hazard_rt_0, hazard_rt_1;
 	logic [4:0] hazard_rs_0, hazard_rs_1;
 	logic [4:0] hazard_write_reg_0, hazard_write_reg_1, hazard_write_reg_2;
@@ -31,30 +30,30 @@ module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=
 	logic [0:0] hazard_flushE, hazard_flushD;
 	// TODO: too many variables - find what should't be here
 	hazard_unit hazard_unit(
-		hazard_m2r_1, hazard_rt_1, hazard_rs_1,
-		hazard_reg_we_1, hazard_write_reg_0, /*>Duplicate but Missing?*/ hazard_m2r_1,
-		hazard_reg_we_2, hazard_write_reg_1, /*>Missing*/ hazard_m2r_2,
-		hazard_reg_we_3, hazard_write_reg_2, // MISSING,
+		B,
 		hazard_rs_0, hazard_rt_0,
-		hazard_branch_taken, hazard_jump_taken,	// NOTE: We aren't doing branch prediction. Can just be control unit branch
-		hazard_forwardAE, hazard_forwardBE,
-		hazard_forwardAD, hazard_forwardBD,	// MISSING
+		hazard_rs_1, hazard_rt_1,
+		hazard_write_reg_0, hazard_reg_we_1, hazard_m2r_1,
+		hazard_write_reg_1, hazard_reg_we_2, hazard_m2r_2,
+		hazard_write_reg_2, hazard_reg_we_3,
+
 		hazard_stallF, hazard_stallD,
-		hazard_flushE, hazard_flushD
+		hazard_forwardAD, hazard_forwardBD,
+		hazard_flushE,
+		hazard_forwardAE, hazard_forwardBE
 	);
 
 	logic [2**width-1:0] pc_addr, pc_addr_1, pc_addr_2;
 	logic [2**width-1:0] pc_addr_write;
 	logic [0:0] pc_we;
 	instruction_counter #(width) PC (clk, rst, ~hazard_stallF, pc_we, pc_addr_write, pc_addr);
-	gatereg #(width, 1) gate_pc_addr(clk, rst, ~hazard_stallF, pc_addr, pc_addr_1); // TODO: Verify if this needs to exist
-	gatereg #(width, 1) gate_pc_addr_1(clk, rst | (hazard_branch_taken | hazard_jump_taken), ~hazard_stallD, pc_addr_1, pc_addr_2);
+	gatereg #(width, 1) gate_pc_addr(clk, rst | hazard_flushD, ~hazard_stallF, pc_addr, pc_addr_1);
 
 
 	logic [2**width-1:0] rom_rd;
 	logic [2**width-1:0] instruction, instruction_1;
 	rom #(progsrc, romsz, width) ROM (pc_addr_1[romsz-1:0], rom_rd);
-	gatereg #(width, 1) gate_instruction(clk, rst | (hazard_branch_taken | hazard_jump_taken), ~hazard_stallD, rom_rd, instruction);
+	gatereg #(width, 1) gate_instruction(clk, rst | hazard_flushD, ~hazard_stallD, rom_rd, instruction);
 	gatereg #(width, 1) gate_instruction_1(clk, rst | hazard_flushE, 1'b1, instruction, instruction_1);
 
 
@@ -74,11 +73,10 @@ module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=
 	gatereg #(0, 1) gate_cu_m2r(clk, rst | hazard_flushE, 1'b1, cu_m2r, cu_m2r_1);
 	
 	gatereg #(0, 1) gate_cu_m2r_1 (clk, rst, 1'b1, cu_m2r_1, cu_m2r_2);
-	gatereg #(0, 1) gate_cu_m2r_2 (clk, rst, 1'b1, cu_m2r_2, REGW_MEM_OR_RD);
-
 	gatereg #(0, 1) gate_cu_m2w_1 (clk, rst, 1'b1, cu_m2w_1, MEM_WE);
-	
 	gatereg #(0, 1) gate_cu_rw_1 (clk, rst, 1'b1, cu_rw_1, cu_rw_2);
+	
+	gatereg #(0, 1) gate_cu_m2r_2 (clk, rst, 1'b1, cu_m2r_2, REGW_MEM_OR_RD);
 	gatereg #(0, 1) gate_cu_rw_2 (clk, rst, 1'b1, cu_rw_2, REG_WE);
 	
 	assign hazard_m2r_1 = cu_m2r_2;
@@ -116,7 +114,7 @@ module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=
 	
 	logic [2**width-1:0] sign_ext_imm, rt_imm;
 	sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], sign_ext_imm);
-	gatereg #(width, 1) gate_sign_ext_imm(clk, rst, 1'b1, sign_ext_imm, rt_imm);
+	gatereg #(width, 1) gate_sign_ext_imm(clk, rst | hazard_flushE, 1'b1, sign_ext_imm, rt_imm);
 
 	// Inputs
 	logic [2**width-1:0] alu_in_a, alu_in_b;
@@ -143,15 +141,13 @@ module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=
 	gatereg #(2, 1) gate_alu_flags (clk, rst, 1'b1, alu_flags, alu_flags_1);
 	assign rd_alu = alu_out_2;
 
-	logic [2**width-1:0] new_pc_addr, new_pc_addr_1;
-	assign new_pc_addr = (sign_ext_imm << 2) + pc_addr_2;
-	gatereg #(width, 1) gate_new_pc_addr (clk, rst, 1'b1, new_pc_addr, new_pc_addr_1);
+	logic [2**width-1:0] new_pc_addr;
+	assign new_pc_addr = (sign_ext_imm << 2) + pc_addr_1;
 	
 
-	assign pc_addr_write = new_pc_addr_1;
+	assign pc_addr_write = new_pc_addr;
 	assign pc_we = B & ((hazard_forwardAD ? alu_out_1 : regf_rs) == (hazard_forwardBD ? alu_out_1 : regf_rt));
-	assign hazard_branch_taken = pc_we;
-	assign hazard_jump_taken = pc_we;
+	assign hazard_flushD = pc_we;
 	logic [2**width-1:0] mem_out, mem_out_1;
 	ram #(ramsz, width) RAM (clk, rst, alu_out_1[ramsz-1:0], MEM_WE, alu_in_b, mem_out);
 	gatereg #(width, 1) gate_mem_out (clk, rst, 1'b1, mem_out, mem_out_1);